潮声隔雨深 · 2019年12月28日

ARMv8 Vector table问题

SoC 芯片

目前正在学习ARMv8 Arch Ref Manual.

D1.10.2 Exception vectors有点疑惑：

Table D1-6 定义了一个Vector Table应该具有的items
我们假定一个ARMv8 SOC实现了4个EL：EL0 / EL1 / EL2 / EL3
根据ARMv8 ARM手册：每一个EL，都有自己对应的Vector Table.
那么：
EL0 / EL1 / EL2 / EL3 :它们各自的Vector Table，应该是什么样的？
比如：
(1) EL0的Vector Table：应该有2个Block :
```
     Current Exception level with SP_EL0

     Current Exception level with SP_ELx, x>0
```
(2) EL1的Vector Table：应该有4个Block :
```
     Current Exception level with SP_EL0

     Current Exception level with SP_ELx, x>0

     EL0 that is using AARCH64

     EL0 that is using AARCH32
```
我的理解对吗？

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一知半解 · 2019年12月28日

EL0 does not have a vector table. Only EL1, EL2 and EL3 have vector tables. The location is set by VBAR_EL1, VBAR_EL2 and VBAR_EL3 respectively.

Each vector table has the same format, i.e. 16 entries (1 entry = 128 bytes) grouped into 4 blocks.

Starting from the lowest offset, each block is used for exceptions taken from:

Current Exception level with SP_EL0
Current Exception level with SP_ELx, x>0.
Lower Exception level, where the implemented level immediately lower than the target level is using AArch64
Lower Exception level, where the implemented level immediately lower than the target level is using AArch32

Consider an IRQ from an AArch32 application (EL0) running on an AArch64 OS (EL1), being handled by an AArch64 hypervisor (EL2).

In this case, the exception will be "from AArch32", but the hypervisor must save all the AArch64 states, as they may contain active values for the OS.

Therefore, the exception entry for this case would be: