潮声隔雨深 · 2020年02月23日

Cortex M3 BRCHSTAT usage

I am looking for a way to enhance CM3 performance especially branch. Following is what I found in TRM that BRCHSTAT seems to give user information of current pipeline status and it can be used to enhance CM3 performance.

I am wondering how to do it?

I read this and think BRCHSTAT should be for low speed memory application since controller usually implement prefetch buffer (similar to cache) and BRCHSTAT can be used to prefetch. I understand branch forwarding is beneficial, but how do we use BRCHSTAT? I also do a research that BRCHSTAT are connected to ETM in integration and that is the only information about the usage.

//

The following scenarios show how you can use branch forwarding and the BRCHSTAT control to get the best performance from your memory system. The scenarios focus on the ideal Harvard setup, where instructions execute from ICODE, literals execute from DCODE (unified to ICODE), and stack/heap/application data executes from SYSTEM.

Zero waitstate

Zero waitstate, registered fetch interface (ICODE)

One wait state flash

One wait state flash, registered fetch interface (ICODE)

Two wait states flash.

//*

Another question is what is the "branch backward" mean. I understand branch forwarding, but what is the idea of backwarding?

1 个回答 得票排序 · 时间排序
一知半解 · 2020年02月23日

understand branch forwarding is beneficial, but how do we use BRCHSTAT?

You can use these signals to do some prefetch in your system to improve the performance.

Another question is what is the "branch backward" mean

It means the branch target address is less then the address of this branch instruction.

你的回答