Hello,
Is it possible in real system that Master will send start address 0x01 ?
If Master wants to write only one byte at address 'h1, other addresses what ever value it has then how Master will give request?
HADDR=32'h1, HSIZE=0, HWRITE=1, HBURST=0, HTRANS=NONSEQ. Then what will happen?
Can anyone help me ???
HADDR=32'h1, HSIZE=0, HWRITE=1, HBURST=0, HTRANS=NONSEQ
That series of control signals should ensure that 1 byte is written to address 0x1.
Yes, it is possible.
What will happen ? The slave should sample the data on the relevant byte lane (depending on bus endianness) and only update that byte in the memory map.
For a memory slave I would expect it to support all widths of transfer possible, so this byte update should always be supported, but for a peripheral device it might have specific documented transfer widths supported. If an unsupported width transfer was attempted, the slave could either return an ERROR response, or it could just overwrite the entire destination register, so corrupting adjacent bytes.
