Has anyone come across documentation that tells how to calculate entrance and exit times from low-power modes where the L1 and L2 cache maintain data coherence?
Thanks,
Has anyone come across documentation that tells how to calculate entrance and exit times from low-power modes where the L1 and L2 cache maintain data coherence?
Thanks,
I have no idea. But without beeing more specific, esp. which SoC you are talking about, I doubt you will see any usefull information as such figures depend on so many parameters.
