极术小姐姐 · 2020年02月03日

Is it necessary to flush data cache 2

why it still have to take DCCMVAC, instead of DCCMVAU ?
If a core is configured to work isolatedly, without shareability of these memory space to other cores.
And if it indeed have to flush data cache of modified page table entry, why it still have to take DCCMVAC, instead of DCCMVAU ?
( Sure, it always fails for DCCMVAU applied after table entry modification.)

MMU access the same private/common cache layer with it CPU core, doesn't it ?

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棋子 · 2020年02月03日

MMU.IRGN[1..0] is composited from { bit0, bit6 } of TTBR0. I mis-spell the bit order and result as "Inner Write-through".

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