如何用VERILOG或VHDL写一段代码，实现10进制计数器？麻烦贴下完整代码。
"module counter10(clk,rst,count);
input clk,rst;
output [3:0] count;
reg [3:0] count;
always@(posedge clk)
begin
if(!rst)
count<=0;
else if(count>=4’d9)
count<=0;
else
count<=count+1;
end
endmodule"
