如何用HDL描述四位的全加法器、5分频电路？

"module adder4(a,b,ci,s,co);
input ci;
input [3:0] a,b;
output co;
output [3:0] s;

assign {co,s}=a+b+ci;
endmodule

module div5(clk,rst,clk_out);
input clk,rst;
output clk_out;
reg [3:0] count;

always@(posedge clk)
begin
if(!rst)
begin
count<=0;
clk_out=0;
end
else if(count==3’d5)
begin

 count<=0;
 clk_out=~clk_out;

end
else
count<=count+1;
end
endmodule"