用flip-flop和logic-gate设计一个1位加法器，输入carryin和current-stage，输出carryout和next-stage
用flip-flop和logic-gate设计一个1位加法器，输入carryin和current-stage，输出carryout和next-stage
"carryout=carryin*current-stage；与门
next-stage=carryin’current-stage+carryincurrent-stage’; 与门，非门，或门（或者异或门）
module(clk,current-stage,carryin,next-stage,carryout);
input clk, current-stage,carryin;
output next-stage,carryout;
always@(posedge clk)
carryout<=carryin¤t-stage;
nextstage<="
