It is necessary for the master to complete the transfer completely. Master is providing address and control at each clock cycle then it is possible that master give address that is not in the range of the burst? if so than how slave respond?
It is necessary for the master to complete the transfer completely. Master is providing address and control at each clock cycle then it is possible that master give address that is not in the range of the burst? if so than how slave respond?
如果主站以任何方式破坏协议（例如，发信号通知错误的地址），则从站的响应不确定。
您不需要设计每个主机和每个从机就能够安全地响应任何可能的非法输入序列，因为这将大大增加系统门数，会增加延迟，从而使您难以满足更大设计的时序要求，并且在您尝试测试所有可能的非法情况时都会给您带来验证梦night。
因此，基本要求是所有主机和从机必须完全遵守协议的要求，正确响应任何可能的合法输入序列，因此您不必担心“如果...怎么办”。
