棋子 · 2020年01月20日

Is there any scenario where HWDATA

I couldnt find any examples as such, as far as I've seen, the two data in the busses HWDATA and HRDATA are never used at the same time as other. Is there any scenario where in one time cycle, the HWDATA holds the data of the current transfer while HRDATA holds the data of the previous transfer.

Also, I need to add/encorporate AHB interface to a processor with Load/Store Architecture that has already been designed. But the processor has only data bus for both input and output. Is it possible to still add AHB interface by multiplexing or two separate data bus port must be present?

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极术小姐姐 · 2020年01月20日

AHB transfers are either read OR write accesses, so you can't have both at the same time. Only one of HRDATA or HWDATA will be getting used in any bus cycle.

There are 2 separate data busses specified as a shared data bus would require turnaround cycles or phases when you need to change transfer directions to avoid driver clashes, and this isn't complexity or latency you would want (it is what the ASB protocol had - the predecessor to AHB - so going back a long time).

So if you add a shared data bus, this wouldn't be AHB compliant, and adds lots of setup/hold complexities for drivers at each end.

As for your existing processor design, you will need to generate separate data buses from the internal shared one. At least there the timing complexity is just something for the local master interface logic to resolve, rather than something all bus components have to meet.

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