棋子 · 2020年01月20日

When should APB slave Sample address

I am working on design of APB master and slave connected back to back. Slave component has simple reg with 16 locations

As per APB, for READ/WRITE transaction from master I am generating PSEL = 1 in the first clock cycle and then PENABLE = 1 in the next clock cycle.

During the two clock cycles, PADDR, PWDATA, PWRITE signals does not change. Here APB slave drives PREADY always HIGH. So the PENABLE goes to '0' in the second clock cycle as per the protocol.

Question here is when should APB slave SAMPLE the Control/Data Signals from Master for both READ/WRITE transfers ? Is it in the SETUP phase or the ACCESS phase.

We need to drive the PREADY and PSLVERR and the PRDATA from slave at the same clock for the read transfer (which should happen in the ACCESS phase here).

Hope my query is clear here. Please share inputs.

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极术小姐姐 · 2020年01月20日

Control signals should be sampled by the peripheral at the end of the setup phase.

For write transfers the peripheral can then sample PWDATA either at the end of the setup phase (when PSEL=1 and PENABLE=0) or else at the end of the access phase (when PSEL=1 and PENABLE=1). PWDATA is guaranteed to be stable throughout the APB access, so it doesn't really matter when you sample it, although I suppose sampling at the end of the access phase is the intention of the protocol as it allows the peripheral one cycle to detect the transfer and then another cycle to then prepare to sample the data.

For read transfers the PRDATA bus is only valid during the access phase, so when PSEL=1 and PENABLE=1 (and PREADY=1), so the master will only sample read data just before PENABLE goes low at the end of the access.

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