I have one AXI module. from upper side master is doing transaction W/R. for master data bus width is 256bits. transaction comes into module and module split that into 2.> bcoz lower side are two 128 bits databus width slaves. upperbits of data bus WDATA[255:128] goes to slave 1 and lowerbits of data bus WDATA[127:0] goes to slave 2. same for WSTRB[32:16] connected to slave 1 & WSTRB[15:0] connected to slave 2.
But in my unit level testing there are 3 protocol checkers. 1 for master and 2 for slave 1& 2. When master initiates the transaction it does not throw any error. but for slave it is throwing error : Write strobes must only be asserted for the correct byte lanes as determined from start address, transfer size and beat number.
Question: how should wstrb & awaddr & awsize & awlen & awburst work for slave 1 and slave 2. as they are half the data bus width.
