Can someone please explain what is Bye Invariance in AXI spec?
As I understood it just says that AXI does not modify the order of send/received bites. It it right?
Thanks
Can someone please explain what is Bye Invariance in AXI spec?
As I understood it just says that AXI does not modify the order of send/received bites. It it right?
Thanks
No, it means that regardless of the bus endianness, the data being transferred will appear on the same byte lanes of the data bus. This makes it simpler to mix big and little endian data in a larger data structure.
So as an example, if you are accessing address 0x0 with a 16-bit transfer on a 32-bit data bus, the data will always appear on D[15:0]. The endianness of the system then defines the order of the bytes on D[15:0], with a little endian byte invariant transfer transferring the LSB on D[7:0] and a big-endian byte invariant transfer using D[15:8] for the LSB.
The alternative to byte invariance is word invariance.
For word invariant transfer in the above example, a little endian transfer would use D[15:0], and a big endian transfer would use D[31:16]. For word invariant the order of the individual bytes within the wider data transfer do not change, only the position of the complete data on the bus.
Endianness is a complex thing that I always find difficult to understand (little endian is the only one that makes sense to me), and endianness isn't something that ARM has created, so usually the best sources of information on this are various sites on the web that will explain what endianness means.
