How do you confirm if a slave is sampling on positive edge of clock only ? How can we prove this in simulation
How do you confirm if a slave is sampling on positive edge of clock only ? How can we prove this in simulation
If you have full access to the AXI3 slave RTL code in your simulation either look at when registers update, or simply manually review the RTL code looking for falling edge triggered code structures.
If you don't have full access, perhaps just a simulation model only, you would need to hopefully see external events occurring soon after falling edges, so not a guaranteed approach.
But why is this a concern for you ?
If the AXI3 slave is 3rd party IP, they wouldn't be AXI3 compliant if they sampled any input on the falling edge of the clock, so would have to make this clear in their documentation, requiring that the AXI3 master and interconnect logic then meets much tighter timing constraints to meet half clock cycle timing paths. That alone should be enough to persuade any slave designer to not do exactly this !
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