What would happen if HREADY will be lower not after address phase, but according to HW internal logic that wants to hold CPU for some clock cycles.
Thanks
What would happen if HREADY will be lower not after address phase, but according to HW internal logic that wants to hold CPU for some clock cycles.
Thanks
As what you describe does not form a legitimate state transition in the AMBA specification, there is no common defined response to this for either a master, any connected slaves, or the interconnect itself. Some plausible outcomes are that the master waits (based on what it sees on the wire interface), or that the master just assumes and responds as though HREADY is HIGH (as it might anticipate from the specification). However, there is no guarantee that the master would do either of these, some strange combination of both, or something completely undocumented.
If downstream logic requires to stall/wait the bus, then it must first sample and hold the address, and de-assert HREADY in the data-phase only.
