It is necessary for the master to complete the transfer completely. Master is providing address and control at each clock cycle then it is possible that master give address that is not in the range of the burst? if so than how slave respond?
It is necessary for the master to complete the transfer completely. Master is providing address and control at each clock cycle then it is possible that master give address that is not in the range of the burst? if so than how slave respond?
If the master breaks the protocol in any way (for example signalling an incorrect address), the slave's response is undefined.
You don't want to have to design every master and every slave to be able to safely respond to ANY possible illegal input sequence as that will massively increase the system gate count, will add latency as you then struggle to meet timings for the larger designs, and will give you a validation nightmare as you try to test every possible illegal scenario.
So the fundamental requirement is that all masters and slaves MUST fully comply with the requirements of the protocol, responding correctly to ANY possible legals input sequence, and then you don't have to worry about "what if...".
Hope that answers some of your questions.
