且将新火试新茶，深究趁年华：STA之RC Corner再论

Q：为什么dpt之后多了ccworst跟ccbest？

A：@Fred ccbest和ccworst的出现是因为dpt同层metal分两张mask，两张mask的alignment误差会导致两张mask上相邻的走线的间距变化，而造成电容的变化。

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Q：在《抽刀断水水更流，RC Corner不再愁：STA之RC Corner》中说电阻跟spacing无关，在《一曲新词酒一杯，RC Corner继续飞: STA之RC Corner拾遗》又说电阻跟spacing有关，为什么电阻跟spacing就相关了？

A：就电阻本身是跟spacing没有无关的，但在半导体制造过程中，因为铜软，所以在dishing时会把铜线切掉一些，这跟那个范围的金属线密度相关，而且这个关系好像也不是线性的。线的密度不同，会使得制造过程对线的厚度造成的影响不同，线厚度被改变了，那阻值自然被改变了。在QRC抽RC的时候会把这一效应模拟成『电阻率=f(W,S)』。 这一效应在foundry给的工艺文件里有相应的描述。

@SteveB 后端角度？如果讲RC 后端抽怎么考虑，讲好原理以后剩下的就是按照RC corner 加上温度抽，交给工具。如果想要知道原理，有几个方面可以去考虑，也是一般后端拿到新工艺需要去研究的:

• 对于寄生参数提取，相关的各个工具的技术文件怎么来？
• 每个corner下的配合PVT signoff里的T趋势如何，是否可以对signoff做精简 ？
• double pattern multiple pattern 的影响如何？
• 研究DFM。

当然还有其他，我这里想到比较能自己去学的有这些。

在《一曲新词酒一杯，RC Corner继续飞: STA之RC Corner拾遗》dishing的图放错了，原文不能修改，在这里一并改过。

Variationin resistivity is caused by a number of phenomena. Copper is a softer materialthan the dielectric in which it is embedded. As a result, the polishing of thewafer during the CMP process has a tendency to remove a little extra copperfrom the top of the wire. This effect is called dishing because of the shape ofthe resulting wire top. The effect becomes more pronounced as the wire widthincreases. This effect is shown in exaggerated form in following pic.

图片来自Quantus QRC Techgen Reference Manual

Q：RC-Corner跟PVT怎么组合？

A：通常的组合：

Q：通常说的ttcorner指的是啥？

A：@孟时光 ttcorner是指管子在tt+RCtyp吧。

Typesof corners

When working in the schematic domain, weusually only work with frontend of line(FEOL) process corners as these corners willaffect the performance of devices. But there is an orthogonal set of processparameters that affectback endof line (BEOL) parasitics.

FEOL corners

One naming convention for process corners isto use two-letter designators, where the first letter refers to the N-channel MOSFET (NMOS) corner, and the second letter refers to the P channel (PMOS)corner. In this naming convention, three corners exist: typical, fast and slow. Fast and slow corners exhibit carrier mobilities that are higher and lower than normal,respectively. For example, a corner designated as FS denotes fast NFETs and slow PFETs.

There are therefore five possible corners:typical-typical (TT) (not really a corner of an n vs. p mobility graph, butcalled a corner, anyway), fast-fast (FF), slow-slow (SS), fast-slow (FS), andslow-fast (SF). The first three corners (TT, FF, SS) are called even corners,because both types of devices are affected evenly, and generally do notadversely affect the logical correctness of the circuit. The resulting devicescan function at slower or faster clock frequencies, and are often binned as such. The last two corners (FS, SF) are called "skewed"corners, and are cause for concern. This is because one type of FET will switchmuch faster than the other, and this form of imbalanced switching can cause oneedge of the output to have much less slew than the other edge. Latching devices may then record incorrect values in the logic chain.

BEOL corners

In addition to the FETs themselves, there are more on-chip variation (OCV) effects thatmanifest themselves at smaller technology nodes. These include process, voltageand temperature (PVT) variation effects on on-chip interconnect, as well as viastructures.

Extraction tools often have a nominal corner to reflect the nominal cross section of the process target.Then the corners cbest and cworst were created to model the smallest andlargest cross sections that are in the allowed process variation. A simplethought experiment shows that the smallest cross section with the largestvertical spacing will produce the smallest coupling capacitance. CMOS Digitalcircuits were more sensitive to capacitance than resistance so this variationwas initially acceptable. As processes evolved and resistance of wiring becamemore critical, the additional rcbest and rcworst werecreated to model the minimum and maximum cross sectional areas for resistance.But the one change is that cross sectional resistance is not dependent on oxidethickness (vertical spacing between wires) so for rcbest the largest is used and for rcworst the smallest is used.

Parameters

Mostimportantly, the corners of a process are designated by five parameters

• Mobility variation due to implantation of N+ and P+
• Vthvariation
• Resistance of the actives
• Bodycoefficient
• Oxidethickness

Otherparameters like the effective Length, effective width, Cjsw caps, Cj caps alsochange.

注：所以TT corner并不是一个需要sign-off的corner。

Q：dishing可以理解成过度刻蚀嘛？

A：@孟时光 不是刻蚀，意思差不多，就多啃掉了一块

Q：为什么铜软？

A：@孟时光 Cu相对氧化硅比较软。大概是：刀子能划铜板，不能划玻璃。

Q：@LZH 有没懂的大牛 scan 下这个问题可以autofix吗？

图片来自@LZH

A：@junbojia最好不用Autofix， 如果D10 Vio比较多的话， autofix不知道会给你fix成什么样子， autofix会对后端产生一些影响，比如timing,routing.

• 建议1：分析一下电路， 看能否再RTL上休掉，如果rtl能修最好rtl修。
• 建议2：不修，这类vio 容易造成mismatch，但是现在ATPG算法能够处理这种情况，避免生成这类pattern。 可能会使patter count受影响。
• 建议3：一般scan insertin都不建议开autofix， 如果要开autofix，插完链以后，report一下都插入了哪些autofix，分析一下合理不。关于autofix DRC，一般不建议开。 但是C家有一个feature， 通过autofix来加入提高coverage，和隔离x-source，具说很好用，但是要advance license。

Q：RTL难修怎么办？

A：那就不修，交给atpg处理。

Q：不修，那对atpg影响是什么？

A：这类vio 容易造成mismatch， 但是现在ATPG算法能够处理这种情况，避免生成这类pattern。 可能会使patter count受影响。

Q：@松泉石 问问C家timingsignoff tools，大家有使用的么？

A：Innovus+TSO应该 很多用 innovus 做16以下的项目的人都用过吧

Q：@松泉石我今天遇到一个问题： sdf annotation completed, 0 Errors, 比较多的Warning，结果vcs 出现 Segmentation fault

A：@占少君 limit stacksize unlimited

Q：@Lauque 问一个问题，怎么理解eFUSE？

A：@wbefuse就是一次性烧入不可更改的rom，每个row有一个bit用来指示是否该row已被烧入，烧入前需要输入一串固定的码这个码应该是efuse厂家提供的 匹配之后才能烧入。

@唐欣 EFUSE理解成保险丝，烧断之前逻辑是1，烧断之后逻辑是0

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PVT+RC corner已又三篇文章，建议详细阅读之，争取详尽的把这个问题说清楚，如果还有疑问欢迎入群深刻讨论。

巴山夜雨涨秋池，邀君共学PVT：STA之PVT

抽刀断水水更流，RC Corner不再愁：STA之RC Corner

一曲新词酒一杯，RC Corner继续飞: STA之RC Corner拾遗

作者：陌上风骑驴
来源：https://mp.weixin.qq.com/s/-9Vd3NUUdRUiFNxvZlESFA
作者微信公众号

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